There are several schemes to achieve low power consumption during low power mode (e.g., sleep mode). One such scheme is clock gating. In clock gating, clock is stopped from toggling during low power mode, and as such, dynamic capacitance is reduced which results in reducing power consumption. Compared to just clock gating, significant amount of leakage power can be saved by putting a processor core (or group of circuitries) into a sleep state, when the processor core (or the group of circuitries) is idle, by powering off its voltage supply. To ensure correct operation of the processor core, when the processor core comes out of sleep state or low power mode, data in critical control/data-path registers need to be preserved during sleep. However, preserving data during sleep with minimal impact to the performance of the processor core is a challenge.